Previously, most personal computer systems utilized circuit boards with components connected by a pin in hole PIH processes. Pins extending from PIH components were inserted into copper plated holes through the circuit board. The PIH components were permanently connected by moving the board over a molten wave of solder with the bottom of the board in contact with the wave so that solder was drawn up into the pin holes to form a metal joint. Also, most integrated chips came in dual in line package (DIP). Such packages were molded plastic containing a chip wire bonded to a lead base from which leads extended out of two longer opposite sides of the package and down in two rows on opposite elongate edges of the module. Empty sockets for PIH DIP packages were provided for adding additional memory chips and for more expensive, complex parts such as microprocessors.
More recently, the more advanced processors of the popular 80X86 family were usually provided in pin grid array (PGA) packages. PGA's were used because processor modules require more input/output connections than other common modules. Pins of a PGA extend from the flat, square bottom surface in a two dimensional array of four or more rows of pins. Although PGA components were also originally developed for mounting in through holes, it became popular to produce computer systems with connection assemblies such as zero insertion force ZIF sockets that allow PGA processor modules to be easily replaced. Such systems could be upgraded simply by replacing a module on the circuit board. For example, many 80486 based personal computer systems allowed the 80486 chip carrier to be replaced with a higher speed 80486 module or even specially made advanced modules. More recently new generations of central processing units are being introduced at an unprecedented rate and it has become popular to provide new generations of processors which are compatible with system boards of previous generations. This also provides a market for new processor modules as soon as they become available. For example, at the time of introduction common P6 modules were compatible with many mother boards originally designed for PENTIUM.TM. (PGA) modules.
Today circuit board manufacturers are moving toward surface mount (SM) technology in which component leads are soldered to pads on a surface of a circuit board. This allows higher density connection since connection pads can be spaced at closer centers than holes, and allows opposite sides of the circuit board to be utilized for components. One popular type of surface mount component for high input/output I/O modules is the quad flat pack.
U.S. Pat. Nos. 5,387,120 and 5,120,238 suggest connectors that allow easily replacing quad flat packs during testing/burn-in and alleges that such connectors may be useful for other types of packages. In these patents, the connector assembly "includes a latch plate pivotally connected to an end of the connector and a hook part pivotally connected to an opposite end of the cover or latch plate."
U.S. Pat. Nos. 4,699,593, 4,744,009 4,768,973, and 4,832,612 suggest an assembly to test a chip carrier (8) connected to flexible circuit (6). The flexible circuit is attached to protective carrier (2) with a hole in which the carrier loosely fits. An interposer (30) connected to substrate (40) has posts (38) over which the protective carrier fits. A bias means compresses contacts of the flexible circuit (6) against contacts (24) of the interposer during test and burn-in. In '973 the bias means is a retaining plate (70), in '009 and '612 the bias means is a pressure plate (42).
U.S. Pat. No. 5,397,245, 5,468,157 and 5,468,158 disclose interconnect system for burn-in testing to produce known good die KGD. '157 suggests a carrier assembly "includes a substrate (17) having a compliant membrane (20b), a plurality of contact bumps (24) containing oxide-penetrating particles on the top surface of the compliant membrane (20b), a fence (30) attached to the top surface of the compliant membrane (20b) for positioning the semiconductor device (21) so that the bond pads on the semiconductor device (21) are aligned with the contact bumps 24." The assembly also includes posts 29b, biasing means, biasing clip 36, and base 42. In '157 the biasing means is a pressure screw and in '158 biasing means is a rotary latch with rotary ramps and a coil spring 60. Oxide penetrating particles are suggested in U.S. Pat. No. 5,083,697.
U.S. Pat. No. 5,052,481 suggests various biasing springs between a cold plate and heat sink, holding a heat sink against the back of a flip chip.
U.S. Pat. Nos. 4,729,809 and 5,163,837 suggest anistropically conductive films and '837 suggests apparatus "to clamp the component (20) to the circuit (12) with the connecter sheet (30) therebetween.
"Process for Producing Palladium Structures" IBM Technical Disclosure Bulletin, Vol. 14, No 1A, June 1981, describes a process for producing dendrites. U.S. Pat. Nos. 4,328,286 and 5,185,073 describe electro-deposition of Pd dendrites. U.S. Pat. No. 5,358,906 describes a chip with bonding pads coated with dendrites. U.S. Pat. No. 5,313,097 describes a memory module with chip connection pads coated with dendrites onto which balls of a flip chip are pressed and then the chips are clamped in place by a heat sink. Anonymous, "New Products Test Interposer" Research Disclosure, January 1990, Number 309 (Denneth Mason Publications Ltd., England) describes a test interposer pads coated with dendrites. "Encapsulated Dendrite Electrical Interconnect for Surface Mount Applications" by P. Arrowsmith et al, IBM Technical Disclosure Bulletin, Vol.38, No 08, August 1995, suggests encapsulating the connection between a gull wing leaded component and dendrite coated connection pads on a printed circuit board. "Double-Sided, Replaceable, Dendrite-Plated Interposer for Connector Applications" by Frankeny et. al., IBM Technical Disclosure Bulletin, Vol. 37, No 10, October 1994, suggests plating the lands of plated through holes of an interposer. U.S. Pat. No. 5,420,520 suggests a "chip test fixture system has contacts corresponding to the contacts on the semiconductor chip."The carrier contacts of '520 have dendritic surfaces."